R&D Engineering, Architect

Job summary

WE ARE Syn*** IS THE LEADER IN ENGINEERING SOLUTIONS FROM SILICON TO SYSTEMS, ENABLING CUSTOMERS TO RAPIDLY INNOVATE AI-POWERED PRODUCTS. WE DELIVER INDUSTRY-LEADING SILICON DESIGN, IP, SIMULATION AND ANALYSIS SOLUTIONS, AND DESIGN SERVICES.

Benefits

Qualifications

• YOU ARE
• You have debugged enough bring-up failures to know that the issue is almost never where it first appears, and you are the person who stays with the waveform until the actual root cause shows itself.
• You are comfortable working across RTL, firmware, and board-level hardware without losing sight of what the customer is actually trying to validate.
• doc to start building.
• You talk to the IP team, the emulation team, and the customer, then you go build the thing that connects all three worlds.
• At Syn***, you will work on Speed Adapter solutions that enable the most advanced system-level validation in the industry.
• The protocols are cutting edge, the customers are the ones defining the next generation of silicon, and what you build will directly determine whether their chip works when it comes back from the fab.
• WHAT YOU'LL BE DOING
• Design and develop Speed Adapter solutions for PCIe Gen5/Gen6, CXL 2.0/3.x, UCIe, and AXI protocols that bridge real-world high-speed I/O with designs running on ZeBu emulation and HAPS prototyping platforms
• Implement protocol logic and speed adaptation functionality on FPGA-based platforms, managing the translation layer between multi-gigabit real-world interfaces and reduced-speed DUTs
• Develop and debug RTL, firmware, and system-level components across the full Speed Adapter stack, from transceiver configuration to protocol state machines to host integration
• Collaborate with IP teams, emulation platform engineers, and prototyping teams to deliver integrated system-level validation solutions that customers can deploy in their labs

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